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02046-DSH-003-F mindspeed technologies? august 2005 mindspeed proprietary and confidential m02046-15/-25 3.3/5v limiting amplifier for applications to 1.25 gbps applications ? 1.06 gbps fibre channel 1.25 gbps ethernet 1.25 gbps sdh/sonet the m02046 is a highly integrated high-gain limiting amplifier that can be used with the same board layout and foot- print as the mc2046-2 (refer to 02046 -app-004-x where x is the revision whic h will change if the application note is revised). featuring pecl outputs, the m02046 is intended for use in applications to 1.25 gbps. full output swing is achieved even at minimum input sensitivity. the m02046 can operate with a 3.3v or 5v supply. included in the m02046 is a programmable signal-level de tector, allowing the user to set thresholds at which the logic outputs are enabled. the signal detect function has typi cally 2 db (optical) of hysteresis which prevents chatter at low input levels. a squelch function, which turns off the outp ut when no signal is present, is provided by externally connecting the los status output to the jam input. the m02046-15 has a cmos status output and the m02046-25 has a pecl status output. both versions have a cmos los output. other available solutions: m02040-15 3.3/5v limiting amplifier for applications to 2.125 gbps (pecl outputs) m02050-15 3.3/5v limiting amplifier for applications to 2.5 gbps (pecl outputs) m02049-15 3.3/5v limiting amplifier for applications to 4.3 gbps (cml outputs) m02043-15 3.3/5v limiting amplifier for applications to 4.3 gbps (cml outputs) typical applications diagram optional limiting amplifier comparator dinn dinp offset cancel output buffer threshold setting circuit regulator v cc st set v cc3 biasing i ref jam los ac-coupled to tia r st v tt level detect st t i a photodiode +3.3 v mon m02016 12.1 k pecln peclp ac or dc coupled (as described in applications information) clock data recovery unit features pin compatible with the mc2046-2 operates with a 3.3v or 5v supply 2.8 mv typical input sensitivity at 1.25 gbps programmable input-s ignal level detect on-chip dc offset cancellation circuit cmos and pecl signal detect output variants output jam function low power (< 200 mw (m02046-15) at 3.3v including pecl load)
02046-DSH-003-F mindspeed technologies? ii mindspeed proprietary and confidential typical eye diagram pin configuration ordering information part number package operating temperature m02046-15* cmos status output (cmos los output) in qsop16 package ?40 c to 85 c m02046-25* pecl status output (cmos los output) in qsop16 package ?40 c to 85 c m02046-15evm evaluation board with m02046-15 (cmos status output) ?40 c to 85 c m02046-25evm evaluation board with m02046-25 (pecl status output) ?40 c to 85 c * the letter ?g? designator after the part number indicates that the d evice is rohs-compliant. refer to www.mindspeed.com for a dditional information. revision history revision level date asic revision description f final july 2005 -15 correct jam connection in bl ock diagram and typical applications figures. correct i ref figure (reference current generation). e final june 2005 -15 in the dc specifications, update r in diff and added note 4. in the ac specifi- cations update v los and dj. updated r st values and the typical los curve ( figure 4-2 - figure 4-4 ). added typical hysteresis curve ( figure 4-5 ). d preliminary april 2005 -15 corrected the asic revision number in this table. update the absolute maximum specification for i(los) and i(st cmos ). add the following dc specification: i ol_cmos . c preliminary march 2005 -15 corrected the device part numbers in the ordering information. update the following dc specifications: r in diff, v oh_cmos , v ol_pecl and v ih . update the following ac specifications: v in(min) , v n , v los , hys, dj, rj, t r /t f , t los_on , and t los_off . update r st values for this revision of the part. added typical applications circuit and eye. 10 mv pp differential input 1.25 gbps 160 mv/div 140 ps/div m02046-x5 date code 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 gnd jam dinp set st v cc3 dinn nc v cc3 nc gnd st los pecln peclp v cc i ref note: x is either a 1 or 2 as explained in the order- ing information above
02046-DSH-003-F mindspeed technologies? 1 mindspeed proprietary and confidential 1.0 product specification 1.1 absolute maximum ratings these are the absolute maximum ratings at or beyond which the ic can be expected to fail or be damaged. reliable operation at these extremes for any length of time is not implied. 1.2 recommended operating conditions table 1-1. absolute maximum ratings symbol parameter rating units v cc power supply voltage (v cc -gnd) -0.5 to +5.75 v t stg storage temperature -65 to +150 c peclp, pecln, st pecl pecl output pins voltage v cc - 2 to v cc + 0.4 v i(peclp), i(pecln), i(st pecl ) pecl output pins maximum continuous current (delivered to load) 30 ma |dinp - dinn| data input pins differential voltage 0.80 v dinp, dinn data input pins voltage meeting |dinp - dinn| requirement gnd to v cc3 + 0.4 v st set signal detect threshold setting pin voltage gnd to v cc3 + 0.4 v jam output enable pin voltage gnd to v cc + 0.4 v st cmos , los cmos status output pins voltage gnd to v cc + 0.4 v i ref current into reference input +0 to -120 a i(los), i(st cmos ) current into cmos status output pins +3000 to -100 a table 1-2. recommended operating conditions parameter rating units power supply: (v cc -gnd) (apply no potential to v cc3 ) or (v cc3 -gnd) (connect v cc to same potential as v cc3 ) +5v 7.5% or +3.3v 7.5% v junction temperature -40 to +110 c operating ambient -40 to +85 c
product specification 02046-DSH-003-F mindspeed technologies? 2 mindspeed proprietary and confidential 1.3 dc characteristics v cc = +3.3v 7.5% or +5v 7.5%, t a = -40c to +85c, unless otherwise noted. typical specifications are for v cc = 3.3v, t a = 25c, unless otherwise noted. table 1-3. dc characteristics symbol parameter conditions min typ max units i cc supply current pecl outputs un-loaded ? 26 38 ma v outhpecl pecl output high voltage (1 ) (peclp, pecln) single ended; 50 ? load to v cc - 2v v cc -1.025 v cc -0.952 v cc -0.88 v v outlpecl pecl output low voltage (1 ) (peclp, pecln) single ended; 50 ? load to v cc - 2v v cc -1.81 v cc -1.71 v cc -1.62 v r in diff differential input resistance m easured between dinp and dinn 90 110 130 ? v oh_cmos cmos st (2 ) , los (2, 3 ) output high voltage external 4.7-10 k ? pull up to v cc 2.75 v cc ?v v ol_cmos cmos st (2 ) , los (2, 3 ) output low voltage external 4.7-10 k ? pull up to v cc 0?0.4v i ol_cmos cmos st (2 ) , los (2, 3 ) output low current (into device) v ol determined by external pull up to v cc ??2.0ma v oh_pecl pecl st output high voltage (1, 3, 4 ) st terminated 50 ? to v cc - 2v v cc -1.115 v cc -1.042 v cc -0.97 v v ol_pecl pecl st output low voltage (1, 3, 4 ) st terminated 50 ? to v cc - 2v v cc -1.88 v cc -1.78 v cc -1.69 v v ih jam input high voltage 2.7 ? v cc v v il jam input low voltage ? ? 0.8 v notes: 1. limits apply between 0c to +85c. belo w 0c the minimum decreases by up to 40 mv. 2. m02046-15 3. m02046-25 4. when st is terminated with a 510 ? resistor to ground, the st output vo ltages are approximately the same as for v outhpecl and v outlpecl
product specification 02046-DSH-003-F mindspeed technologies? 3 mindspeed proprietary and confidential 1.4 ac characteristics v cc = +3.3v 7.5% or +5v 7.5%, t a = -40c to +85c, input bit rate = 2.5 gbps 2 23 -1 prbs unless otherwise noted. typical specifications are for v cc = 3.3v, t a = 25c, unless otherwise noted. table 1-4. ac characteristics symbol parameter conditions min typ max units v in(min) differential input sensitivity 1.25 gbps, ber < 10 -12 ?2.85mv v i(max) input overload ber < 10 -12 , differential input 1.25 gbps 1200 ? ? mv ber < 10 -12 , single-ended input, 1.25 gbps 600 ? ? mv v n rms input referred noise ? 200 ? v rms v los los programmable range differential inputs 5 ? 55 mv hys signal detect/los hysteresis (electri cal); across los programmable range 2 3.5 5.5 db bw lf small-signal ?3db low frequency cutoff excluding ac coupling capacitors ? 25 ? khz dj deterministic jitter (includes dcd) k28.5 pattern at 1.25 gbps, 10 mvpp input ? 18 70 ps rj random jitter 10 mv pp input ? 5 ? ps rms t r / t f data output rise and fall times 20% to 80%; outputs terminated into 50 ?; 10 mv pp input ? 150 230 ps t los_on time from los state until los output is asserted los assert time after 1 v pp input signal is turned off; signal detect level set to 10 mv 2.3 ? 80 s t los_off time from non-los state until los is deasserted los deassert time after input crosses signal detect level; signal detect set to 10 mv with applied input signal of 20 mv pp 2.3 ? 80 s figure 1-1. data input requirements dinp dinn 2 - 600 mv 4 - 1200 m v differential input single-ended input dinp or dinn 4 - 600 mv unused input
product specification 02046-DSH-003-F mindspeed technologies? 4 mindspeed proprietary and confidential note: for single-ended input connections. when connecting to the used input with ac-coupling, the unused input should be ac-coupled through 50 ? to the supply voltage of the tia; when connecting to the used input with dc-coupling, the unused input should be dc-coupled through 50 ? to a voltage equal to the common mode level of the used input. figure 1-2. typical a pplications circuit note: ac-coupled inputs shown. optional limiting amplifier comparator dinn dinp offset cancel output buffer threshold setting circuit regulator v cc st set v cc3 biasing i ref jam los ac-coupled to tia r st v tt level detect st t i a photodiode +3.3 v mon m02016 12.1 k pecln peclp ac or dc coupled (as described in applications information) clock data recovery unit
02046-DSH-003-F mindspeed technologies? 5 mindspeed proprietary and confidential 2.0 pin definitions table 2-1. pin descriptions qsop pin# name function 1st set loss of signal threshold setting input. conn ect a 1% resistor between this pin and v cc3 (pin 2) to set loss of signal threshold. 2v cc3 power supply input for 3.3v applications or the output of the internally regulated 3.3v voltage when v cc = 5v. connect directly to supply for 3.3v applications (interna l regulator not in use). do not connect to power supply if v cc = 5v. 3 gnd ground. 4 dinp non-inverting data input. internally terminated with 50 ? to v tt (see figure 3-2 ). 5 dinn inverting data input. internally terminated with 50 ? to v tt (see figure 3-2 ). 6 nc no connect. leave floating. 7v cc3 power supply input for 3.3v applications or the output of the internally regulated 3.3v voltage when v cc = 5v. connect directly to supply for 3.3v applications (interna l regulator not in use). do not connect to power supply if v cc = 5v. 8 jam output disable. when high, data outputs are disabled (with non-inverting out put held high and inverting output held low). connect to los output to di sable outputs with loss of signal. out puts are enabled when jam is low or floating. internal 150 k ? resistor to ground. 9 los loss of signal output. goes high when i nput signal falls below threshold set by st set . this output is an open collector ttl with internal 80 k ? pull-up resistor to v cc . leave floating if not used. 10 st signal detect output. goes high when input si gnal amplitude is above threshold set by st set . in m02046-15, this output is an open collector ttl with internal 80 k ? pull-up resistor to v cc ; in m02046-25, this output is pecl. leave floating if not used. 11 gnd ground. 12 pecln inverting data output (pecl). 13 peclp non-inverting data output (pecl). 14 v cc power supply. connect to either +5v or +3.3v. 15 nc no connect. leave floating. 16 i ref internal reference current for the los threshold. must be connected to ground through a 12.1 k ? 1% resistor.
pin definitions 02046-DSH-003-F mindspeed technologies? 6 mindspeed proprietary and confidential figure 2-1. m02046-x5 pinout m02046-x5 date code 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 gnd jam dinp set st v cc3 dinn nc v cc3 nc gnd st los pecln peclp v cc i ref note: x is either a 1 or 2 as explained in the ordering information
02046-DSH-003-F mindspeed technologies? 7 mindspeed proprietary and confidential 3.0 functional description 3.1 overview the m02046 is a highly integrated high-gain limiting amplifier that can be used with the same board layout and footprint as the mc2046-2. featuring pecl outputs, the m02046 is intended for use in applications to 1.25 gbps. full output swing is achieved even at minimum input sensitivity. the m02046 can operate with a 3.3v or 5v supply. included in the m02046 is a programmable signal-level dete ctor, allowing the user to set thresholds at which the logic outputs are enabled. the signal detect function has typically 2 db (optical) of hysteresis which prevents chatter at low input levels. a squelch fu nction, which turns off the output when no signal is present, is provided by externally connecting the los status output to the jam input. the m02046-15 has a cmos status output and the m02046-25 has a pecl status output. both versions have a cmos los output. figure 3-1. block diagram example level detect limiting amplifier comparator dinn dinp pecln peclp offset cancel output buffer threshold setting circuit regulator v cc st set v cc3 biasing i ref jam v tt st los
functional description 02046-DSH-003-F mindspeed technologies? 8 mindspeed proprietary and confidential 3.2 features pin compatible with the mc2046-2 operates with a 3.3v or 5v supply 2.8 mv typical input sensitivity at 1.25 gbps programmable input-signal level detect on-chip dc offset cancellation circuit cmos and pecl signal detect output variants output jam function low power (< 200 mw (m02046-15) including pecl outputs) 3.3 general description the m02046 is a high-gain limiting amplifier for applications up to 1.25 gbps, and incorporates a limiting amplifier, an input signal level detection circuit and also a fully integrated dc-offset cancellation loop that does not require any external components. the m02046 features a pecl high-speed data outputs. the m02046 provi des the user with the flexibility to set the signal det ect threshold and feat ures either a cmos status output (m02046-15) or a pecl status output (m020 46-25). optional output buffer disable (squelch/jam) can be implemented using the jam input. 3.3.1 inputs the data inputs are internally connected to v tt via 50 ? resistors, and generally need to be ac coupled. referring to figure 3-2 , the nominal v tt voltage is 2.85v because of the internal resistor divider to v cc3 , which means this is the dc potential on the data inputs. see the applications information section for further details on choosing the ac- coupling capacitor. figure 3-2. cml data inputs v cc3 50 dinp v tt 50 dinn 8.3 k 1.3 k v cc v cc
functional description 02046-DSH-003-F mindspeed technologies? 9 mindspeed proprietary and confidential 3.3.2 dc offset compensation the m02046 contain an internal dc autozero circuit that can remove the effect of dc offsets without using external components. this circuit is configured such that the feedback is effective only at frequencies well below the lowest frequency of interest. the low frequency cut off is typically 25 khz. 3.3.3 data outputs the m02046 features 100k/300k pecl compliant outputs as shown in figure 3-3 . the outputs may be terminated using any standard ac or dc-coupling pecl termination te chnique. ac-coupling is used in applications where the average dc content of the data is zero e.g. sonet. the advantage of this approach is lower power consumption, no susceptibility to dc drive and compatibility with no n-pecl interfaces. 3.3.4 signal detect (st) and loss of signal (los) the m02046 features input signal level detection over an extended range. using an external resistor, r st , between pin st set and v cc3 ( figure 3-6 ) the user can program the input signal threshold. the signal detect status is indicated on the both the signal detect (st) and los output pins. the status output is either cmos (m02046-15) or pecl (m02046-25). the pecl version is shown in figure 3-4 while figure 3-5 shows the st output for the cmos version of the device (and the los output for both versions of the device). the st (los) signal is active (not asserted) when the signal is above the threshold value. the signal detection circuitry has the equivalent of 3.5 db (typical) electrical hysteresis. figure 3-3. pecl data outputs v cc v cc - 2v 50 50 peclp pecln
functional description 02046-DSH-003-F mindspeed technologies? 10 mindspeed proprietary and confidential r st establishes a threshold voltage at the st set pin as shown in figure 3-6 . internally, the input signal level is monitored by the level detector which creates a dc voltage proportional to the input signal peak to peak value. the voltage at st set is internally compared to the signal level from the level detector. when the level detect voltage is less than v (stset) , los is asserted and will stay asserted until the input signal level increases by a predefined amount of hysteresis. when the input level increases by more than this hysteresis above v (stset) , los is deasserted. see the applications information section for the selection of r st . note that st set can be left open if the loss of signal detector f unction is not required. in this case los would be low. figure 3-4. pecl st output (m02046-25) figure 3-5. cmos st (m02046-15) and los (m02046-15 and m02046-25) output st v cc v cc - 2v 50 either los o r st v cc 80 k
functional description 02046-DSH-003-F mindspeed technologies? 11 mindspeed proprietary and confidential 3.3.5 jam function when asserted, the active high power down (jam) pin forces the outputs to a logic ?one? state. this ensures that no data is propagated through the system. the loss of signal detection circuit can be used to automatically force the data outputs to a high state when the input signal falls below the threshold. the function is normally used to allow data to propagate only when the signal is above the us er's bit-error-rate requirement. it therefore inhibits the data outputs toggling due to noise when there is no signal present (?squelch?). in order to implement this function, los should be connected to the jam pin shown in figure 3-7 , thus forcing the data outputs to a logic ?one? state when the signal falls below the threshold. 3.3.6 voltage regulation the m02046 contain an on-chip voltage regulator to allow both 5v and 3.3v operation. when used at 5v, the on- chip regulator is enabled and the digital inputs and outputs are compatible with ttl 5v logic levels. figure 3-6. stset input figure 3-7. jam input v cc3 st set r st v stset v cc jam v cc 55 k 100 k
02046-DSH-003-F mindspeed technologies? 12 mindspeed proprietary and confidential 4.0 applications information 4.1 applications 1.06 gbps fibre channel 1.25 gbps ethernet 1.25 gbps sdh/sonet 4.1.1 reference current generation the m02046 contain an accurate on-chip bias circuit that requires an external 12.1 k ? 1% resistor, r ref , from pin i ref to ground to set the los threshold voltage at st set precisely. figure 4-1. reference current generation los v set v lvl_det bg_ref v cc3 r st r ref st set i ref
applications information 02046-DSH-003-F mindspeed technologies? 13 mindspeed proprietary and confidential 4.1.2 connecting v cc and v cc3 for 5v operation, the v cc pin is connected to an appropriate 5v 7.5% supply. no potential should be applied to the v cc3 pin. the only connection to v cc3 should be r st as shown in figure 3-6 . when v cc = 5v all logic outputs and the data outputs are 5v compatible. for low power operation, v cc and v cc3 should be connected to an appropriate 3.3v 7.5% supply. in this case all i/os are 3.3v compatible. 4.1.3 choosing an inpu t ac-coupling capacitor when ac-coupling the input the coupling capacitor should be of sufficient value to pass the lowest frequencies of interest, bearing in mind the number of consecutive identic al bits, and the input resistance of the part. for sonet data, a good rule of thumb is to chose a coupling capacitor that has a cut-off frequency less than 1/(10,000) of the input data rate. for example, for 1.25 gbps data, the coupling capacitor should be chosen as: f cutoff (1.25x10 9 / 10x10 3 ) = 125 khz the -3 db cutoff frequency of the low pass filter at the 50 ? input is found as: f 3db = 1/ (2 * * 50 ? * c ac ) so solving for c where f 3db = f cutoff c ac = 1/ (2 * * 50 ? * f cutoff ) eq.1 and in this case the minimum capacitor is 25 nf. for ethernet or fibre channel, there are less consecutive bits in the data, and the recommended cut-off frequency is 1/(1,000) of the input data rate. this results in a minimum capacitor of 2.5 nf for 1.25 gbps ethernet. multirate applications down to 155 mbps in this case, the input coupling capacitor needs to be large enough to pass 15 khz (155x10 6 /10,000) which results in a capacitor value of 0.2 f. however, because this low pass frequency is close to the 25 khz low pass frequency of the internal dc servo loop, it is preferable to use a larger input coupling capacitor such as 1 f which provides an input cutoff frequency of 3.1 khz. this separates the two poles sufficiently to allow them to be considered independent. this capacitor should also have a 20 nf capacitor in parallel to pass the higher frequency data (in the multirate application) without distortion. in all cases, a high quality coupling capacitor should be used as to pass the high frequency content of the input data stream. 4.1.4 setting the signal detect level using figure 4-2 , the value for r st is chosen to set the los threshold at the desired value. the resulting hysteresis is also shown in figure 4-2 . from figure 4-2 , it is apparent that small variations in r st cause significant variation in the los threshold level, particularly for low input sign al levels. this is because of the logarith mic relationship between the internal level detect voltage and the input signal level. it is recommended that a 1% resistor be used for r st and that allowance is provided for los variation, particularly when the lo s threshold is near the sensitivity limit of the m02046. example r st resistor values are given in table 4-1 .
applications information 02046-DSH-003-F mindspeed technologies? 14 mindspeed proprietary and confidential table 4-1. typical los assert and de-assert levels for various 1% r st resistor values r st (k ? ) vin (mv pp) differential los assert los de-assert 7.50 4.9 7.8 6.81 11.7 17.0 6.19 23.2 33.4 5.49 55.0 77.3 figure 4-2. typical loss of signal char acteristic (full input signal range) r st (k ? ) 0 10 20 30 40 50 60 70 80 5.5 5.7 5.9 6.1 6.3 6.5 6.7 6.9 7.1 7.3 7.5 threshold level (mv pp ) optical hysteresis de-assert assert = 10*log 10 (de-assert/assert) 1.25 gbps, 2 31 - 1 conditions: vcc = 3.3v, temp = 25c
applications information 02046-DSH-003-F mindspeed technologies? 15 mindspeed proprietary and confidential figure 4-3. typical loss of signal char acteristic (low input signal range) figure 4-4. typical loss of signal char acteristic (high input signal range) r st (k ? ) 0 10 20 30 6.56.76.97.17.37.5 threshold level (mv pp ) de-assert assert = 10*log 10 (de-assert/assert) 1.25 gbps, 2 31 - 1 conditions: vcc = 3.3v, temp = 25c optical hysteresis threshold level (mv pp ) r st (k ? ) 0 10 20 30 40 50 60 70 80 5.5 5.7 5.9 6.1 6.3 6.5 optical hysteresis = 10*log 10 (de-assert/assert) 1.25 gbps, 2 31 - 1 conditions: vcc = 3.3v, temp = 25c assert de-assert
applications information 02046-DSH-003-F mindspeed technologies? 16 mindspeed proprietary and confidential 4.1.5 peclp and pecln termination the data outputs of the m02046 are pecl compatible. for the high speed peclp and pecln outputs any standard ac or dc-coupling termination technique can be used. figure 4-6 and figure 4-7 illustrate typical ac and dc terminations. ac-coupling is used in applications where the average dc content of the data is zero e.g. sonet. the advantage of this approach is lower power consumption, no suscept ibility to dc drift and compatibility with non-pecl interfaces. figure 4-6 shows the circuit configuration and table 4-2 lists the resistor values. if using transmission lines other than 50 ? , the shunt terminating resistance z t should equal twice the impedance of the transmission line (z o ). dc-coupling can be used when driving pecl interfaces an d has the advantage of a reduced component count. a thevenin termination is used at the receive end to give a 50 ? load and the correct dc bias. figure 4-7 shows the circuit configuration and table 4-2 the resistor values. alternatively, if available, terminating to v cc - 2v as shown in figure 4-8 has the advantage that the resistance value is the same for 3.3v and 5v operation and it also has performance advantages at high data rates. in the m02046, st is a pecl output. it is recommended that it be dc terminated in a pecl load, preferably as shown in figure 4-8 , but the decoupling capacitor on the load is not required as this is a dc output. figure 4-5. typical loss of signal hysteresi s characteristic (full input signal range) table 4-2. pecl termination resistor values supply output impedance r pull-down z t r ta / r tb r t / r b 5v 50 ? 270 ? 100 ? 2.7 k ? / 7.8 k ? 82 ? / 130 ? 3.3v 50 ? 150 ? 100 ? 2.7 k ? / 4.3 k ? 130 ? / 82 ? 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.7 5.9 6.1 6.3 6.5 6.7 6.9 7.1 7.3 7.5 electrical hysteresis (db) r st (k ? ) 1.25 gbps, 2 31 - 1 conditions: vcc = 3.3v, temp = 25c = 20*log 10 (de-assert/assert) electrical hysteresis
applications information 02046-DSH-003-F mindspeed technologies? 17 mindspeed proprietary and confidential figure 4-6. ac-coupled pecl termination figure 4-7. dc-coupled pecl termination figure 4-8. alternative pecl termination v cc m02046 peclp z o z t r pull-down pecl 0.1f v cc r ta r tb 0.1f r tb r ta pecln z o v cc m02046 z o pecl v cc r t r b r b r t z o 10 nf peclp pecln v cc z o pecl z o 10 nf v cc v cc - 2v 50 50 m02046 peclp pecln
applications information 02046-DSH-003-F mindspeed technologies? 18 mindspeed proprietary and confidential 4.1.6 st pecl (m02046-25) termination the st (in the pecl version of the part) output of the m02046 is pecl swing compatible. in most module applications, it is not common for this output to be terminated into a standard pecl load as shown in figure 4-8 for the data outputs because st is typically in a v oh state and this would consume ~20 ma of continuous supply current. in cases where an alternative termination can be used it is recommended that a single 510 ? resistor be connected between the st output and ground. when this termination is used, the v oh and v ol levels of the st output typically meet the standard defined pecl levels and the swing is within pecl limits. this has the additional advantage of reducing the current consumption due to st being high to <5 ma. 4.1.7 using jam as shown in the typical applications circuit ( figure 1-2 ), the los output pin can optionally be connected to the jam input pin. when los asserts the jam function sets the data outputs to a fixed ?one? state (peclp is held high and pecln is held low). this is normally used to allow data to propagate on ly when the signal is above the users' bit error rate (ber) requirement. it prevents the outputs from toggling due to noise when no signal is present. from the los assert and deassert figures above ( figure 4-2 - figure 4-4 ), when an input signal is below the los assert threshold, los asserts (los high) causing jam to assert. when jam asserts, the data outputs and the internal servo loop of the m02046-x5 are disabled. if the input signal reaches or exceeds the los deassert threshold, los deasserts (los low) causing jam to deassert, and hence enables the data outputs and the internal servo loop. if, however, the input signal is slowly increa sing to a level that does not exceed the los deassert threshold (operating in the hysteresis region), the intern al servo loop may not be fully established and this may cause partial enabling of the data outputs. to avoid this the input signal needs to fully reach or exceed the los deassert level to fully enable the data outputs.
02046-DSH-003-F mindspeed technologies? 19 mindspeed proprietary and confidential 5.0 package specification figure 5-1. package information ee1 bottom view seating plane stand-off a1 stand-off symbol tols/n qsop16 a max. 1.60 a1 .05 0.1 a2 .05 1.40 d .05 4.95 e .10 6.00 e1 .05 3.90 l .15 0.60 ccc max. 0.080 ddd max. 0.10 e basic 0.635 b .025 0.224 c .02 0.22 r .05 0.25 r1 min. 0.20
02046-DSH-003-F mindspeed technologies? 20 mindspeed proprietary and confidential ? 2005, mindspeed technologies tm , inc. all rights reserved. information in this document is provided in connection with mindspeed technologies tm ("mindspeed tm ") products. these materials are provided by mindspeed as a service to its customers and may be used for informational pur- poses only. except as provided in mindspeed?s terms and conditions of sale for such products or in any separate agreement related to this document, mindspeed assu mes no liability whatsoever. mindspeed assumes no respon- sibility for errors or omissions in th ese materials. mindspeed may make ch anges to specifications and product descriptions at any time, without notice. mindspeed makes no commitment to update the information and shall have no responsibility wh atsoever for conflicts or incomp atibilities arising from future changes to its specifications and product descriptions. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. these materials are provided "as is" without warranty of any kind, either express or implied, relating to sale and/or use of mindspeed products including liability or war- ranties relating to fitness for a particular purpose, consequential or incidental dam- ages, merchantability, or infringement of any patent, copyright or other intellectual property right. mindspeed further does not warrant the accuracy or completeness of the information, text, graphics or othe r items contained within these materials. mindspeed shall not be liable for any special, indirect, incidental, or consequential damages, including without limi tation, lost revenues or lost profits, which may result from the use of these materials. mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. mindspeed cus- tomers using or selling mindspeed products for use in such applications do so at thei r own risk and agree to fully indemnify mindspeed for any damages resulting from such improper use or sale.
02046-DSH-003-F mindspeed technologies? 21 mindspeed proprietary and confidential www.mindspeed.com general information: (949) 579-3000 headquarters - newport beach 4000 macarthur blvd., east tower newport beach, ca. 92660

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